Datasheet

Section 7 DMA Controller (DMAC)
R01UH0309EJ0500 Rev. 5.00 Page 369 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
A
ddress T
A
A
ddress B
A
Transfer
Address T
B
Legend:
Address
Address
Address
Address
Where :
Address B
B
= L
A
= L
B
= L
A
+ SAIDE · (–1)
SAID
· (2
DTSZ
· (N – 1))
= L
B
+ DAIDE · (–1)
DAID
· (2
DTSZ
· (N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRA
T
A
T
B
B
A
B
B
L
A
L
B
N
Figure 7.11 Operation in Normal Mode
Transfer requests (activation sources) are external requests, EP1FIFO full interrupt and EP2FIFO
empty interrupt of the USB, and auto-requests. With auto-requests, the DMAC is only activated by
register setting, and the specified number of transfers are performed automatically. With auto-
requests, cycle steal mode or burst mode can be selected. In cycle steal mode, the bus is released
to another bus master each time a transfer is performed. In burst mode, the bus is held
continuously until transfer ends.