Datasheet

Section 7 DMA Controller (DMAC)
Page 366 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
A
ddress T
A
ddress B
Transfer
DAC
K
1 byte or word transfer performed in
response to 1 transfer request
Legend:
Address T = L
Address B = L + (–1)
DTID
· (2
DTSZ
· (N – 1))
Where : L = Value set in MAR
N = Value set in ETCR
Figure 7.9 Operation in Single Address Mode (When Sequential Mode Is Specified)
Figure 7.10 shows an example of the setting procedure for single address mode (when sequential
mode is specified).