Datasheet

Section 7 DMA Controller (DMAC)
R01UH0309EJ0500 Rev. 5.00 Page 359 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Table 7.6 Register Functions in Idle Mode
Function
Register DTDIR = 0 DTDIR = 1 Initial Setting Operation
23 0
MAR
Source
address
register
Destination
address
register
Start address of
transfer destination
or transfer source
Fixed
23 15 0
IOARH'FF
Destination
address
register
Source
address
register
Start address of
transfer source or
transfer destination
Fixed
015
ETCR
Transfer counter Number of transfers Decremented every
transfer; transfer
ends when count
reaches H'0000
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented by a data transfer. IOAR specifies the lower 16 bits of the
other address. The upper 8 bits of IOAR have a value of H'FF.
Figure 7.5 illustrates operation in idle mode.
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
MAR
Figure 7.5 Operation in Idle Mode
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer
ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The
maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmit data empty and receive data full interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can only be specified for channel B.