Datasheet

Section 7 DMA Controller (DMAC)
Page 354 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Table 7.4 DMAC Transfer Modes
Transfer Mode Transfer Source Remarks
Short
address
mode
Dual address mode
• 1-byte or 1-word transfer
for a single transfer
request
• Specify source and
destination addresses to
transfer data in two bus
cycles.
(1) Sequential mode
• Memory address
incremented or
decremented by 1 or 2
• Number of transfers: 1 to
65,536
(2) Idle mode
• Memory address fixed
• Number of transfers: 1 to
65,536
(3) Repeat mode
• Memory address
incremented or
decremented by 1 or 2
• Continues transfer after
sending number of
transfers (1 to 256) and
restoring the initial value
• TPU channel 0 to 5
compare match/input
capture A interrupt
• SCI transmit data
empty interrupt
• SCI receive data full
interrupt
• A/D converter
conversion end
interrupt
• External request
Single address mode
• 1-byte or 1-word transfer
for a single transfer
request
• 1-bus cycle transfer by
means of DACK pin
instead of using address
for specifying I/O
• Sequential mode, idle
mode, or repeat mode can
be specified
• External request
• Up to 4 channels can
operate independently
• External request applies
to channel B only
• Single address mode
applies to channel B
only