Datasheet

Section 7 DMA Controller (DMAC)
Page 350 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
MAR, IOAR, and ETCR can always be written to regardless of the DMAWER settings. When
modifying these registers, the channel to be modified should be halted.
7.3.7 DMA Terminal Control Register (DMATCR)
DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can
be set for output automatically, and a transfer end signal output, by setting the appropriate bit. The
TEND pin is available only for channel B in short address mode. Except for the block transfer
mode, a transfer end signal asserts in the transfer cycle in which the transfer counter contents
reaches 0 regardless of the activation source. In the block transfer mode, a transfer end signal
asserts in the transfer cycle in which the block counter contents reaches 0.
Bit Bit Name Initial Value R/W Description
7, 6 ⎯ All 0 ⎯ Reserved
These bits are always read as 0 and cannot be
modified.
5 TEE1 0 R/W Transfer End Enable 1
Enables or disables transfer end pin 1 (TEND1)
output.
0: TEND1 pin output disabled
1: TEND1 pin output enabled
4 TEE0 0 R/W Transfer End Enable 0
Enables or disables transfer end pin 0 (TEND0)
output.
0: TEND0 pin output disabled
1: TEND0 pin output enabled
3 to 0 ⎯ All 0 ⎯ Reserved
These bits are always read as 0 and cannot be
modified.