Datasheet

Section 7 DMA Controller (DMAC)
Page 348 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
7.3.6 DMA Write Enable Register (DMAWER)
The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the
transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies
restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for
the specific channel, to prevent inadvertent rewriting of registers other than those for the channel
concerned. The restrictions applied by DMAWER are valid for the DTC.
Bit Bit Name Initial Value R/W Description
7 to 4 ⎯ All 0 ⎯ Reserved
These bits are always read as 0 and cannot be
modified.
3 WE1B 0 R/W Write Enable 1B
Enables or disables writes to all bits in DMACR1B,
bits 11, 7, and 3 in DMABCR, and bit 5 in
DMATCR.
0: Writes are disabled
1: Writes are enabled
2 WE1A 0 R/W Write Enable 1A
Enables or disables writes to all bits in DMACR1A,
and bits 10, 6, and 2 in DMABCR.
0: Writes are disabled
1: Writes are enabled
1 WE0B 0 R/W Write Enable 0B
Enables or disables writes to all bits in DMACR0B,
bits 9, 5, and 1 in DMABCR, and bit 4 in
DMATCR.
0: Writes are disabled
1: Writes are enabled
0 WE0A 0 R/W Write Enable 0A
Enables or disables writes to all bits in DMACR0A,
and bits 8, 4, and 0 in DMABCR.
0: Writes are disabled
1: Writes are enabled