Datasheet

Section 7 DMA Controller (DMAC)
R01UH0309EJ0500 Rev. 5.00 Page 345 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Bit Bit Name Initial Value R/W Description
5 DTME0 0 R/W Data Transfer Master Enable 0
Together with the DTE0 bit, this bit controls
enabling or disabling of data transfer on channel
0. When both the DTME0 bit and DTE0 bit are set
to 1, transfer is enabled for channel 0.
If channel 0 is in the middle of a burst mode
transfer when an NMI interrupt is generated, the
DTME0 bit is cleared, the transfer is interrupted,
and bus mastership passes to the CPU. When the
DTME0 bit is subsequently set to 1 again, the
interrupted transfer is resumed. In block transfer
mode, however, the DTME0 bit is not cleared by
an NMI interrupt, and transfer is not interrupted.
[Clearing conditions]
• When initialization is performed
• When NMI is input in burst mode
• When 0 is written to the DTME0 bit
[Setting condition]
When 1 is written to DTME0 after reading DTME0
= 0