Datasheet

Section 7 DMA Controller (DMAC)
R01UH0309EJ0500 Rev. 5.00 Page 335 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Bit Bit Name Initial Value R/W Description
3
2
1
0
DTF3
DTF2
DTF1
DTF0
0
0
0
0
R/W
R/W
R/W
R/W
Data Transfer Factor 3 to 0
These bits select the data transfer factor
(activation source). The factors that can be
specified differ between normal mode and block
transfer mode.
• Normal Mode
0000: Setting prohibited
0001: Setting prohibited
0010: Activated by DREQ pin falling edge input
(detected as a low level in the first transfer
after transfer is enabled)*
0011: When USBDRQE bit in PFCR3 is 0:
Activated by DREQ pin low-level input
When USBDRQE bit in PFCR3 is 1:
Activated by USB interrupt signal low-level
input
010x: Setting prohibited
0110: Auto-request (cycle steal)
0111: Auto-request (burst)
1xxx: Setting prohibited