Datasheet

Section 7 DMA Controller (DMAC)
R01UH0309EJ0500 Rev. 5.00 Page 331 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Bit Bit Name Initial Value R/W Description
3
2
1
0
DTF3
DTF2
DTF1
DTF0
0
0
0
0
R/W
R/W
R/W
R/W
Data Transfer Factor 3 to 0
These bits select the data transfer factor
(activation source). There are some differences in
activation sources for channel A and channel B.
• Channel A
0000: Setting prohibited
0001: Activated by conversion end interrupt of A/D
converter unit 0
0010: Setting prohibited
0011: Setting prohibited
0100: Activated by SCI channel 0 transmit data
empty interrupt
0101: Activated by SCI channel 0 receive data full
interrupt
0110: Activated by SCI channel 1 transmit data
empty interrupt
0111: Activated by SCI channel 1 receive data full
interrupt
1000: Activated by TPU channel 0 compare
match/input capture A interrupt
1001: Activated by TPU channel 1 compare
match/input capture A interrupt
1010: Activated by TPU channel 2 compare
match/input capture A interrupt
1011: Activated by TPU channel 3 compare
match/input capture A interrupt
1100: Activated by TPU channel 4 compare
match/input capture A interrupt
1101: Activated by TPU channel 5 compare
match/input capture A interrupt
1110: Setting prohibited
1111: Setting prohibited