Datasheet

Section 7 DMA Controller (DMAC)
Page 326 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
7.3.1 Memory Address Registers (MARA and MARB)
MAR is a 32-bit readable/writable register that specifies the source address (transfer source
address) or destination address (transfer destination address). MAR consists of two 16-bit registers
MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and
cannot be modified.
The DMA has four MAR registers: MAR_0A in channel 0 (channel 0A), MAR_0B in channel 0
(channel 0B), MAR_1A in channel 1 (channel 1A), and MAR_1B in channel 1 (channel 1B).
MAR is not initialized by a reset or in standby mode.
Short Address Mode: In short address mode, MARA and MARB operate independently.
Whether MAR functions as the source address register or as the destination address register can be
selected by means of the DTDIR bit in DMACR.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
address specified by MAR is constantly updated.
Full Address Mode: In full address mode, MARA functions as the source address register, and
MARB as the destination address register.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
source or destination address is constantly updated.