Datasheet

Section 7 DMA Controller (DMAC)
R01UH0309EJ0500 Rev. 5.00 Page 325 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Table 7.2 Short Address Mode and Full Address Mode (Channel 0)
FAE0 Description
0 Short address mode specified (channels 0A and 0B operate independently)
Channel 0A
MAR_0AH Specifies transfer source/transfer destination address
Specifies transfer destination/transfer source address
Specifies number of transfers
Specifies transfer size, mode, activation source.
Specifies transfer source/transfer destination address
Specifies transfer destination/transfer source address
Specifies number of transfers
Specifies transfer size, mode, activation source.
IOAR_0A
ETCR_0A
DMACR_0A
Channel 0B
MAR_0BH
MAR_0AL
MAR_0BL
IOAR_0B
ETCR_0B
DMACR_0B
1 Full address mode specified (channels 0A and 0B operate in combination as channel 0)
Channel 0
MAR_0AH Specifies transfer source address
Specifies transfer destination address
Not used
Not used
Specifies number of transfers
Specifies number of transfers (used in block transfer
mode only)
Specifies transfer size, mode, activation source, etc.
IOAR_0A
ETCR_0A
DMACR_0A
MAR_0BH
MAR_0AL
MAR_0BL
IOAR_0B
ETCR_0B
DMACR_0B