Datasheet

Section 7 DMA Controller (DMAC)
Page 322 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
A block diagram of the DMAC is shown in figure 7.1.
TGI0A
TGI1A
TGI2A
TGI3A
TGI4A
TGI5A
TXI0
RXI0
TXI1
RXI1
ADI0
USBINTN0
USBINTN1
DREQ0
DREQ1
TEND0
TEND1
DACK0
DACK1
DMTEND0A
DMTEND0B
DMTEND1A
DMTEND1B
DMAWER
DMACR_1B
DMACR_1A
DMACR_0B
DMACR_0A
DMATCR
DMABCR
MAR_0AH
MAR_0BH
IOAR_0A
ETCR_0A
IOAR_0B
ETCR_0B
MAR_1AH
IOAR_1A
ETCR_1A
MAR_1BH
MAR_0AL
MAR_0BL
MAR_1AL
MAR_1BL
IOAR_1B
ETCR_1B
Internal address bus
Address buffer
Processor
Internal interrupts
External pins
Interrupt signals
Control logic
Data buffer
Internal data bus
[Legend]
DMAWER: DMA write enable register
DMATCR: DMA terminal control register
DMABCR: DMA band control register (for all channels)
DMACR: DMA control register
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
Module data bus
Channel 0Channel 1
Channel 0AChannel 0BChannel 1AChannel 1B
Figure 7.1 Block Diagram of DMAC