Datasheet

Section 7 DMA Controller (DMAC)
R01UH0309EJ0500 Rev. 5.00 Page 321 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 7 DMA Controller (DMAC)
This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4
channels.
7.1 Features
• Selectable as short address mode or full address mode
Short address mode
⎯ Maximum of 4 channels can be used
⎯ Dual address mode or single address mode can be selected
⎯ In dual address mode, one of the two addresses, transfer source and transfer destination, is
specified as 24 bits and the other as 16 bits
⎯ In single address mode, transfer source or transfer destination address only is specified as
24 bits
⎯ In single address mode, transfer can be performed in one bus cycle
⎯ Choice of sequential mode, idle mode, or repeat mode for dual address mode and single
address mode
Full address mode
⎯ Maximum of 2 channels can be used
⎯ Transfer source and transfer destination addresses as specified as 24 bits
⎯ Choice of normal mode or block transfer mode
• 16-Mbyte address space can be specified directly
• Byte or word can be set as the transfer unit
• Activation sources: internal interrupt, external request, auto-request (depending on transfer
mode)
⎯ Six compare match/input capture interrupts of 16-bit timer-pulse unit (TPU0 to TPU5)
⎯ Transmit data empty and receive data full interrupts of serial communication interface
(SCI_0, SCI_1)
⎯ Conversion end interrupt of A/D converter (A/D_0)
⎯ EP1FIFO full interrupt and EP2FIFO empty interrupt of USB
⎯ External request
⎯ Auto-request
• Module stop state can be set.