Datasheet

Section 6 Bus Controller (BSC)
Page 314 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
CPU
cycle
External bus released state
External space read
T
1
T
2
φ
Address bus
DQMU, DQML
BREQ
BACK
BREQO
NOP PALL NOP NOP
[1] [2] [3] [5][4] [6]
[8] [7] [9]
[1] Low level of BREQ signal is sampled at rise of φ.
[2] PALL command is issued.
[3] Bus control signal returns to be high at end of external space access cycle.
At least one state from sampling of BREQ signal.
[4] BACK signal is driven low, releasing bus to external bus master..
[5] BREQ signal state is also sampled in external bus released state.
[6] High level of BREQ signal is sampled.
[7] BACK signal is driven high, ending external bus release cycle.
[8] When there is external access or refresh request of internal bus master during
external bus release while the BREQOE bit is set to 1, BREQO signal goes low.
[9] BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO
signal is asserted because of auto-refreshing request, it retains low until auto-refresh cycle starts up.
Data bus
Precharge-sel
WE
RAS
CKE
CAS
SDRAMφ
Row
address
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
Figure 6.97 Bus Release State Transition Timing when Synchronous DRAM Interface
Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454
Group.