Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 307 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
T
p
Address bus
Idle cycle
Data bus
T
r
T
c1
T
c2
DRAM space writeDRAM space read
T
c2
T
i
T
c1
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Note: n = 2 to 5
φ
Figure 6.93 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Write Accesses to DRAM Space in RAS Down Mode