Datasheet

Section 6 Bus Controller (BSC)
Page 306 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Previous Access Next Access ICIS2 ICIS1 ICIS0 DRMI IDLC Idle cycle
0 ⎯ ⎯ ⎯ ⎯ Disabled
1 ⎯ ⎯ ⎯ 0 1 state inserted
Normal space read
1 2 states inserted
0 ⎯ ⎯ ⎯ ⎯ Disabled
1 ⎯ ⎯ ⎯ 0 1 state inserted
Normal space write
DRAM/continuous
synchronous DRAM*
space read
1 2 states inserted
0 ⎯ ⎯ ⎯ ⎯ Disabled
1 ⎯ ⎯ ⎯ 0 1 state inserted
Normal space read
1 2 states inserted
0 ⎯ ⎯ ⎯ ⎯ Disabled
1 ⎯ ⎯ ⎯ 0 1 state inserted
DRAM/continuous
synchronous
DRAM
*
space write
DRAM/continuous
synchronous DRAM*
space read
1 2 states inserted
Note: * Not supported by the H8S/2456 Group and H8S/2454 Group.
Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of
consecutive read and write operations in DRAM/continuous synchronous DRAM space burst
access. Figures 6.93 and 6.94 show an example of the timing for idle cycle insertion in the case of
consecutive read and write accesses to DRAM/continuous synchronous DRAM space.