Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 301 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
T
p
Address bus
φ
RD
RAS
HWR, LWR
U
CAS, LCAS
External address space write
Idle cycle
Data bus
T
r
T
c1
T
c2
T
1
DRAM space readDRAM space read
T
2
T
c2
T
3
T
i
T
c1
Figure 6.89 Example of Idle Cycle Operation after DRAM Access
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)