Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 299 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
T
p
Address bus
Idle cycle
Data bus
T
r
T
c1
T
cl
T
c2
T
3
T
c1
Continuous synchronous
DRAM space read External space read
Continuous synchronous
DRAM space write
T
2
T
i
T
1
RAS
CAS
WE
RD
HWR, LWR
CKE
High
High
PALL ACTV READ
NOP NOPWRIT
DQMU, DQML
T
Cl
T
c2
Precharge-sel
φ
Row
address
Row
address
Column
address
External address
External address
Column address 1 Column address 2
Figure 6.87 Example of Idle Cycle Operation in RAS Down Mode
(Write after Read) (IDLC = 0, CAS Latency 2)