Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 293 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(4) Relationship between Chip Select (CS) Signal and Read (RD) Signal
Depending on the system's load conditions, the RD signal may lag behind the CS signal. An
example is shown in figure 6.80. In this case, with the setting for no idle cycle insertion (a), there
may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals. In the initial state after reset release, idle cycle insertion (b) is set.
T
1
A
ddress bus
φ
RD
Bus cycle A
T
2
T
3
T
1
T
2
Bus cycle B
Overlap period between CS (area B)
and RD may occur
(a) No idle cycle insertion
(ICIS1 = 0)
T
1
Address bus
Idle cycle
φ
Bus cycle A
T
2
T
3
T
i
T
1
Bus cycle B
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
T
2
CS (area A)
CS (area B)
RD
CS (area A)
CS (area B)
Figure 6.80 Relationship between Chip Select (CS) and Read (RD)