Datasheet

Section 6 Bus Controller (BSC)
Page 288 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
T
1
Upper address bus
Lower address bus
φ
CSn
AS
Data bus
T
2
T
3
T
1
T
2
T
1
Full access
T
2
RD
Burst access
Note: n = 1 and 0
Figure 6.75 Example of Burst ROM Access Timing
(ASTn = 1, 2-State Burst Cycle)