Datasheet

Section 6 Bus Controller (BSC)
Page 286 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(2) Read Data Extension
If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is read-
accessed in DMAC/EXDMAC single address mode, the establishment time for the read data can
be extended by clock suspend mode. The number of states for insertion of the read data extension
cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR. Be sure to set the OEE bit to 1 in
DRAMCR when the read data will be extended. The extension of the read data is not in
accordance with the bits DDS and EDDS.
Figure 6.74 shows the timing chart when the read data is extended by two cycles.
Address bus
φ
SDRAM
φ
Column address
Row
address
Row
address
Column
address
Data bus
T
p
T
r
T
c2
T
cl
T
sp2
T
sp1
T
c1
RAS
CAS
WE
CKE
PALL ACTV
NOPREAD
DQMU, DQML
D
ACK or EDACK
Precharge-sel
Figure 6.74 Example of Timing when the Read Data Is Extended by Two States
(DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2)