Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 285 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
T
p
φ
SDRAMφ
RAS
Read
CAS
WE
CKE
PALL ACTV READ NOP
DQMU, DQML
Data bus
Address bus
T
r
T
c1
T
cl
T
c2
Row address Column address Column address
Precharge-sel
Row address
High
RAS
Write
CAS
WE
CKE
PALL ACTV NOP NOPWRIT
DQMU, DQML
DACK or RDACK
Data bus
High
Figure 6.73 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0