Datasheet

Section 6 Bus Controller (BSC)
Page 268 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
T
p
SDRAMφ
φ
RAS
CAS
WE
CKE
PALL ACTV READ NOP
DQMU
DQML
Lower data bus
Upper data bus
Address bus
T
r
T
c1
T
cl
T
c2
Row address Column address Column address
Precharge-sel
Row address
High
High
High impedance
Figure 6.62 DQMU and DQML Control Timing
(Lower Byte Read Access: CAS Latency 2)