Datasheet

Section 6 Bus Controller (BSC)
Page 264 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
6.8.9 Precharge State Count
When the interval specification from the PALL command to the next ACTV/REF command
cannot be satisfied, from one to four T
p
states can be selected by setting bits TPC1 and TPC0 in
DRACCR. Set the optimum number of T
p
cycles according to the synchronous DRAM connected
and the operating frequency of this LSI. Figure 6.59 shows the timing when two Tp states are
inserted.