Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 263 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
6.8.8 Row Address Output State Control
When the command interval specification from the ACTV command to the next READ/WRIT
command cannot be satisfied, 1 to 3 states (Trw) that output the NOP command can be inserted
between the Tr cycle that outputs the ACTV command and the Tc1 cycle that outputs the column
address by setting the RCD1 and RCD0 bits of DRACCR. Use the optimum setting for the wait
time according to the synchronous DRAM connected and the operating frequency of this LSI.
Figure 6.58 shows an example of the timing when the one Trw state is set.
T
p
SDRAMφ
RAS
Read
CAS
WE
CKE
PALL ACTV NOP READ NOP
DQMU, DQML
Data bus
Address bus
T
r
T
rw
T
c1
T
cl
T
c2
Row address
Column
address
Column address
Precharge-sel
Row address
High
RAS
Write
CAS
WE
CKE
PALL ACTV NOP NOPWRIT
DQMU, DQML
Data bus
High
φ
Figure 6.58 Example of Access Timing when Row Address Output Hold State Is 1 State
(RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2)