Datasheet

Section 6 Bus Controller (BSC)
Page 260 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
T
p
SDRAMφ
RAS
Read
CAS
WE
CKE
PALL ACTV READ NOP
DQMU, DQML
Data bus
Address bus
φ
T
r
T
c1
T
c2
Row address Column address Column address
Precharge-sel
Row address
High
RAS
Write
CAS
WE
CKE
PALL ACTV NOP WRIT
DQMU, DQML
Data bus
High
Figure 6.56 Basic Access Timing of Synchronous DRAM (CAS Latency 1)