Datasheet

Page xxix of xxx
23.5.1 Notes on Clock Pulse Generator......................................................................... 1211
23.5.2 Notes on Resonator............................................................................................. 1211
23.5.3 Notes on Board Design ....................................................................................... 1212
Section 24 Power-Down Modes ......................................................................1213
24.1 Register Descriptions....................................................................................................... 1217
24.1.1 Standby Control Register (SBYCR) ................................................................... 1217
24.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) .................. 1219
24.1.3 Extension Module Stop Control Registers H and L
(EXMSTPCRH, EXMSTPCRL) ........................................................................ 1220
24.1.4 RAM Module Stop Control Registers H and L
(RMMSTPCRH, RMMSTPCRL)....................................................................... 1221
24.2 Operation ......................................................................................................................... 1223
24.2.1 Clock Division Mode.......................................................................................... 1223
24.2.2 Sleep Mode ......................................................................................................... 1224
24.2.3 Software Standby Mode...................................................................................... 1225
24.2.4 Hardware Standby Mode .................................................................................... 1228
24.2.5 Module Stop Function ........................................................................................ 1231
24.2.6 All Module Clocks Stop Mode ........................................................................... 1232
24.3 φ Clock Output Control.................................................................................................... 1233
24.4 SDRAMφ Clock Output Control ..................................................................................... 1234
24.5 Usage Notes ..................................................................................................................... 1235
24.5.1 I/O Port Status..................................................................................................... 1235
24.5.2 Current Dissipation during Oscillation Stabilization Standby Period................. 1235
24.5.3 EXDMAC, DMAC, and DTC Module Stop....................................................... 1235
24.5.4 On-Chip Peripheral Module Interrupts ............................................................... 1235
24.5.5 Writing to MSTPCR, EXMSTPCR, and RMMSTPCR...................................... 1235
24.5.6 Notes on Clock Division Mode........................................................................... 1236
Section 25 List of Registers.............................................................................1237
25.1 Register Addresses (Address Order)................................................................................ 1238
25.2 Register Bits..................................................................................................................... 1254
25.3 Register States in Each Operating Mode ......................................................................... 1274
Section 26 Electrical Characteristics ...............................................................1289
26.1 Electrical Characteristics for H8S/2456 Group and H8S/2456R Group .......................... 1289
26.1.1 Absolute Maximum Ratings ............................................................................... 1289
26.1.2 DC Characteristics .............................................................................................. 1290
26.1.3 AC Characteristics .............................................................................................. 1294
26.1.4 A/D Conversion Characteristics ......................................................................... 1302