Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 259 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
6.8.5 Synchronous DRAM Clock
The synchronous clock (SDRAMφ) is output from the CS5 pin. SDRAMφ is shifted by 90° phase
from φ. Therefore, a stable margin is ensured for the synchronous DRAM that operates at the
rising edge of clocks. Figure 6.55 shows the relationship between φ and SDRAMφ.
SDRAMφ
φ
T
cyc
1/4 T
cyc
(90°)
Figure 6.55 Relationship between φ and SDRAMφ
6.8.6 Basic Timing
The four states of the basic timing consist of one T
p
(precharge cycle) state, one T
r
(row address
output cycle) state, and the T
c1
and two T
c2
(column address output cycle) states.
When areas 2 to 5 are set for the continuous synchronous DRAM space, settings of the WAITE bit
of BCR, RAST, CAST, RCDM bits of DRAMCR, and the CBRM bit of REFCR are ignored.
Figure 6.56 shows the basic timing for synchronous DRAM.