Datasheet

Section 6 Bus Controller (BSC)
Page 250 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
DRAM space write
TR
c3
TR
p1
TR
p2
T
p
T
r
Software
standby
T
c1
T
c2
Note: n = 2 to 5
RASn (CSn)
UCAS, LCAS
OE (RD)
WE (HWR)
Data bus
A
ddress bus
φ
Figure 6.52 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States