Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 249 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
T
Rp
T
Rr
UCAS, LCAS
Software
standby
T
Rc3
HWR (WE)
CSn (RASn)
φ
Note: n = 2 to 5
High
Figure 6.51 Self-Refresh Timing
In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately
after self-refreshing is longer than the normal precharge time. A setting can be made in bits
TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1
to 7 states longer than the normal precharge time. In this case, too, normal precharging is
performed according to the setting of bits TPC1 and TPC0 in DRACCR, and therefore a setting
should be made to give the optimum post-self-refresh precharge time, including this time. Figure
6.52 shows an example of the timing when the precharge time immediately after self-refreshing is
extended by 2 states.