Datasheet

Section 6 Bus Controller (BSC)
Page 240 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
T
p
T
r
T
c1
T
c2
T
c3
T
c1
T
c2
T
c3
RASn (CSn)
Read
Write
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
Address bus
φ
Note: n = 2 to 5
Row address Column address 1 Column address 2
High
High
Figure 6.43 Operation Timing in Fast Page Mode
(RAST = 0, CAST = 1)
The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion
method and timing are the same as for full access. For details see section 6.7.9, Wait Control.