Datasheet

Page xxvii of xxx
19.2 Input/Output Pins............................................................................................................. 1097
19.3 Register Descriptions....................................................................................................... 1097
19.3.1 D/A Data Registers 2 and 3 (DADR2 and DADR3)........................................... 1097
19.3.2 D/A Control Register 23 (DACR23) .................................................................. 1098
19.4 Operation ......................................................................................................................... 1100
19.5 Usage Notes ..................................................................................................................... 1102
19.5.1 Module Stop Function Setting ............................................................................ 1102
19.5.2 D/A Output Hold Function in Software Standby Mode...................................... 1102
Section 20 Synchronous Serial Communication Unit (SSU) ..........................1103
20.1 Features............................................................................................................................ 1103
20.2 Input/Output Pins............................................................................................................. 1105
20.3 Register Descriptions....................................................................................................... 1106
20.3.1 SS Control Register H (SSCRH) ........................................................................ 1107
20.3.2 SS Control Register L (SSCRL) ......................................................................... 1109
20.3.3 SS Mode Register (SSMR)................................................................................. 1110
20.3.4 SS Enable Register (SSER) ................................................................................ 1111
20.3.5 SS Status Register (SSSR).................................................................................. 1112
20.3.6 SS Control Register 2 (SSCR2) .......................................................................... 1114
20.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................. 1116
20.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................. 1117
20.3.9 SS Shift Register (SSTRSR)............................................................................... 1117
20.4 Operation ......................................................................................................................... 1118
20.4.1 Transfer Clock .................................................................................................... 1118
20.4.2 Relationship of Clock Phase, Polarity, and Data ................................................ 1118
20.4.3 Relationship between Data Input/Output Pins and Shift Register ...................... 1119
20.4.4 Communication Modes and Pin Functions ......................................................... 1120
20.4.5 SSU Mode........................................................................................................... 1122
20.4.6 SCS Pin Control and Conflict Error.................................................................... 1133
20.4.7 Clock Synchronous Communication Mode ........................................................ 1134
20.5 Interrupt Requests ............................................................................................................ 1141
20.6 Usage Note....................................................................................................................... 1142
20.6.1 Module Stop Function Setting ............................................................................ 1142
Section 21 RAM ..............................................................................................1143
Section 22 Flash Memory ................................................................................1145
22.1 Memory Map ................................................................................................................... 1147
22.2 Register Descriptions....................................................................................................... 1148
22.2.1 Flash Memory Control Register 1 (FLMCR1).................................................... 1149