Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 237 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
This LSI
(Address shift size
set to 10 bits)
RASn (CSn)
2-CAS type 16-Mbit DRAM
1-Mbyte × 16-bit configuration
10-bit column address
RAS
UCAS UCAS
LCAS LCAS
HWR (WE) WE
RD (OE) OE
A9 A8
A10 A9
A8 A7
A7 A6
A6 A5
A5 A4
A4 A3
A3 A2
A2 A1
A1 A0
D15 to D0
D15 to D0
Row address input:
A9 to A0
Column address input:
A9 to A0
Figure 6.41 Example of 2-CAS DRAM Connection