Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 229 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
6.7.6 Column Address Output Cycle Control
The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit
to 1 in DRAMCR. Use the setting that gives the optimum specification values (CAS pulse width,
etc.) according to the DRAM connected and the operating frequency of this LSI. Figure 6.34
shows an example of the timing when a 3-state column address output cycle is selected.
T
p
RASn (CSn)
Read
Write
UCAS, LCAS
WE
(HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
Address bus
φ
T
r
T
c1
T
c2
T
c3
Row address Column address
High
High
Note: n = 2 to 5
Figure 6.34 Example of Access Timing with 3-State Column Address Output Cycle
(RAST = 0)