Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 223 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
6.7 DRAM Interface
In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing
performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM
space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst
operation is also possible, using fast page mode.
6.7.1 Setting DRAM Space
Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The
relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.5.
Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), four areas (areas 2
to 5), and continuous area (areas 2 to 5).
Table 6.5 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space
RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2
0 1 Normal space Normal space Normal space DRAM space
0 Normal space Normal space DRAM space DRAM space
0
1
1 DRAM space DRAM space DRAM space DRAM space
0 Continuous synchronous DRAM space
*
0
1 Mode register settings of synchronous DRAM
*
0 Reserved (setting prohibited)
1
1
1 Continuous
DRAM space
Continuous
DRAM space
Continuous
DRAM space
Continuous
DRAM space
Note: * Reserved (setting prohibited) in the H8S/2456 Group and H8S/2454 Group.
With continuous DRAM space, RAS2 is valid. The bus specifications (bus width, number of wait
states, etc.) for continuous DRAM space conform to the settings for area 2.