Datasheet

Section 6 Bus Controller (BSC)
Page 222 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
When consecutively reading from the same area connected to a peripheral LSI whose output
floating time is long, data outputs from the peripheral LSI may conflict with address outputs from
this LSI. The data conflict can be avoided by inserting the CS assertion period extension cycle
after the access cycle. Figure 6.32 shows an example of the operation. In the figure, both bus
cycles A and B are read access cycles to the same area which is address/data multiplexed I/O
space. (a) shows an example of conflict occurring between data outputs from the peripheral LSI
whose output floating time is long and address outputs from this LSI because the CS assertion
period extension cycle is not inserted. (b) shows an example of the data conflict being avoided by
inserting the CS assertion period extension cycle.
Bus cycle A
Address/data
bus
Bus cycle B
Output floating
time is long
Data conflict
(b) With CS assertion period extension cycle
(CSXTn = 1)
AH
RD
CS
Bus cycle A Bus cycle B
WR
RD
CS
φ
Address bus
φ
Address bus
Address/data
bus
(a) Without CS assertion period extension cycle
(CSXTn = 0)
Figure 6.32 Consecutive Read Accesses to Same Area
(Address/Data Multiplexed I/O Space)