Datasheet

Section 6 Bus Controller (BSC)
Page 220 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(2) Data Cycle
In the data cycle, program wait insertion and pin wait insertion by the WAIT pin are enabled in the
same way as in the basic bus interface. For details, refer to section 6.5.4, Wait Control. Wait
control settings do not affect the address cycles.
6.6.7 Read Strobe (RD) Timing
In the address/data multiplexed I/O interface, the read strobe timing of data cycles can be modified
in the same way as in the basic bus interface. For details, refer to section 6.5.5, Read Strobe (RD)
Timing. Figure 6.30 shows an example when the read strobe timing is modified.
AD15 to AD8
AD15 to AD8
RDNn = 0
RDNn = 1
CSn
AH
RD
RD
Tma1 T1 T2Tma2
Address cycle Data cycle
φ
Address bus
Address
Address
Read
data
Note: n = 6, 7
Read
data
Figure 6.30 Example of Read Strobe Timing