Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 219 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
6.6.6 Wait Control
(1) Address Cycle
A single address wait cycle Tmaw can be inserted between Tma1 and Tma2 cycles by setting the
ADDEX bit in MPXCR to 1. Figure 6.29 shows the access timing when the address cycle is three
cycles.
AD15 to AD8
AD7 to AD0
AD15 to AD8
AD7 to AD0
CSn
AH
RD
HWR
LWR
Tma1 Tmaw Tma2 T1 T2
Address cycle Data cycle
φ
Address bus
Write
Read
Address
Address
Read
data
Write data
Notes: 1. n = 6, 7
2. When RDNn = 0
Address
Address
Figure 6.29 Example of Access Timing with Address Wait