Datasheet

Section 6 Bus Controller (BSC)
Page 214 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
CSn
AH
RD
HWR
LWR
AD15 to AD8
AD7 to AD0
AD15 to AD8
AD7 to AD0
Tma1 Tma2 T1 T2
Address cycle Data cycle
φ
Address bus
Write
Read
Address
Address
Read
data
Write data
Notes: 1. n = 6, 7
2. When RDNn = 0
Address
Address
Figure 6.24 Bus Timing for 16-Bit, 2-State Data Access Space
(Odd Address Byte Access)