Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 213 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(3) 16-Bit, 2-State Data Access Space
Figures 6.23 to 6.25 show bus timings for a 16-bit, 2-state data access space. When a 16-bit access
space is accessed, the entire address bus (AD15 to AD0) is used for all addresses, and the upper
half (AD15 to AD0) of the data bus is used for even addresses and the lower half (AD7 to AD0) of
the data bus is used for odd addresses. Wait states cannot be inserted in the data cycle.
CSn
AH
RD
HWR
LWR
AD15 to AD8
AD7 to AD0
AD15 to AD8
AD7 to AD0
Tma1 Tma2 T1 T2
Address cycle Data cycle
φ
Address bus
Write
Read
Address
Address
Read
data
Write data
Notes: 1. n = 6, 7
2. When RDNn = 0
Address
Address
Figure 6.23 Bus Timing for 16-Bit, 2-State Data Access Space (Even Address Byte Access)