Datasheet

Section 6 Bus Controller (BSC)
Page 212 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(2) 8-Bit, 3-State Data Access Space
Figure 6.22 shows the bus timing for an 8-bit, 3-state data access space. When an 8-bit access
space is accessed, the upper halves (AD15 to AD8) of both the address bus and data bus are used.
Wait states can be inserted in the data cycle.
CSn
AH
RD
HWR
LWR
AD15 to AD8
AD15 to AD8
Tma1 Tma2 T1 T2 T3
Address cycle Data cycle
φ
Address bus
Write
Read
Address
Address
Read
data
Write data
Notes: 1. n = 6, 7
2. When RDNn = 0
Figure 6.22 Bus Timing for 8-Bit, 3-State Data Access Space