Datasheet

Section 6 Bus Controller (BSC)
Page 210 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
6.6.3 Data Bus
The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access
space or 16-bit access space by the ABW7 and ABW6 bits in ABWCRA. For the 8-bit access
space, AD15 to AD8 are valid for both address and data. For the 16-bit access space, AD15 to
AD0 are valid for both address and data. If the address/data multiplexed I/O space is accessed, the
corresponding address will be output to the address bus. For details on access size and data
alignment, see section 6.5.1, Data Size and Data Alignment.
6.6.4 Address Hold Signal
In the address/data multiplexed I/O space, a hold signal (AH) that indicates the timing for latching
the address is output. The AH output pin is multiplexed with the AS output pin. When the external
address space is specified as the address/data multiplexed I/O space, the multiplexed pin functions
as the AH output pin. Note however that the multiplexed pin will function as the AS output pin
until the address/data multiplexed I/O space is specified.
6.6.5 Basic Timing
The bus cycle in the address/data multiplexed I/O interface consists of an address cycle and a data
cycle. The data cycle is based on the basic bus interface timing specified by ABWCR, ASTCR,
WTCRAH, RDNCR, and CSACR.