Datasheet

Section 6 Bus Controller (BSC)
Page 208 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
6.5.6 Extension of Chip Select (CS) Assertion Period
Some external I/O devices require a setup time and hold time between address and CS signals and
strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert
states in which only the CS, AS, and address signals are asserted before and after a basic bus space
access cycle. Extension of the CS assertion period can be set for individual areas. With the CS
assertion extension period in write access, the data setup and hold times are less stringent since the
write data is output to the data bus.
Figure 6.20 shows an example of the timing when the CS assertion period is extended in basic bus
3-state access space.
T
h
Address bus
φ
T
1
T
2
T
3
T
t
Bus cycle
Data bus
HWR, LWR
Write
Data bus
RD
CSn
AS
Read
(when
RDNn = 0)
Read data
Write data
Figure 6.20 Example of Timing when Chip Select Assertion Period Is Extended