Datasheet

Section 6 Bus Controller (BSC)
Page 200 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Invalid
D7 to D0
Valid
Read
HWR
LWR
D15 to D8
D7 to D0
Valid
Write
High
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space
(Odd Address Byte Access)