Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 199 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(3) 16-Bit, 2-State Access Space
Figures 6.12 to 6.14 show bus timings for a 16-bit, 2-state access space. When a 16-bit access
space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the
lower half (D7 to D0) for odd addresses. Wait states cannot be inserted.
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
Write
High
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)