Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 197 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
6.5.3 Basic Timing
(1) 8-Bit, 2-State Access Space
Figure 6.10 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is
accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high.
Wait states can be inserted.
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
High impedance
Write
High
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space