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ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 144 (20x20) 16-Bit 32 MHz I/O number 96
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Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 191 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
6.4.3 Memory Interfaces
The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of
ROM, SRAM, and so on; an address/data multiplexed I/O interface that allows direct connection
of peripheral LSIs that require address/data multiplexing, a DRAM interface that allows direct
connection of DRAM; a synchronous DRAM interface that allows direct connection of
synchronous DRAM; and a burst ROM interface that allows direct connection of burst ROM. The
interface can be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space. An area for
which the address/data multiplexed I/O interface is designated functions as address/data
multiplexed I/O space, an area for which the DRAM interface is designated functions as DRAM
space, an area for which the synchronous DRAM interface is designated functions as continuous
synchronous DRAM space, and an area for which the burst ROM interface is designated functions
as burst ROM space.
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode.
Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454
Group.
(1) Area 0
Area 0 includes on-chip ROM in expanded mode with on-chip ROM enabled and the space
excluding on-chip ROM is external address space, and in expanded mode with on-chip ROM
disabled, all of area 0 is external address space.
When area 0 external space is accessed, the CS0 signal can be output.
Either the basic bus interface or burst ROM interface can be selected for the memory interface of
area 0.
(2) Area 1
In externally expanded mode, all of area 1 is external address space.
When area 1 external address space is accessed, the CS1 signal can be output.
Either the basic bus interface or burst ROM interface can be selected for the memory interface of
area 1.