Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 189 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
6.4.2 Bus Specifications
The external address space bus specifications consist of five elements: bus width, number of
access states, number of program wait states, read strobe timing, and chip select (CS) assertion
period extension states. The bus width and number of access states for on-chip memory and
internal I/O registers are fixed, and are not affected by the bus controller.
(1) Bus Width
A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is
selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions
as a 16-bit access space. If all areas are designated as 8-bit access space, 8-bit bus mode is set; if
any area is designated as 16-bit access space, 16-bit bus mode is set.
(2) Number of Access States
Two or three access states can be selected with ASTCR. An area for which 2-state access is
selected functions as a 2-state access space, and an area for which 3-state access is selected
functions as a 3-state access space. With the DRAM or synchronous DRAM interface and burst
ROM interface, the number of access states may be determined without regard to the setting of
ASTCR.
When 2-state access space is designated, wait insertion is disabled. When 3-state access space is
designated, it is possible to insert program waits by means of the WTCRA and WTCRB, and
external waits by means of the WAIT pin.
Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454
Group.
(3) Number of Program Wait States
When 3-state access space is designated by ASTCR, the number of program wait states to be
inserted automatically is selected with WTCRA and WTCRB. From 0 to 7 program wait states can
be selected. Table 6.2 shows the bus specifications (bus width, and number of access states and
program wait states) for each basic bus interface area.