Datasheet

Page xxi of xxx
12.4.7 Inverted Pulse Output ........................................................................................... 818
12.4.8 Pulse Output Triggered by Input Capture............................................................. 819
12.5 Usage Notes ....................................................................................................................... 820
12.5.1 Module Stop Function Setting .............................................................................. 820
12.5.2 Operation of Pulse Output Pins............................................................................. 820
Section 13 8-Bit Timers (TMR).........................................................................821
13.1 Features.............................................................................................................................. 821
13.2 Input/Output Pins...............................................................................................................823
13.3 Register Descriptions......................................................................................................... 824
13.3.1 Timer Counter (TCNT)......................................................................................... 825
13.3.2 Time Constant Register A (TCORA).................................................................... 825
13.3.3 Time Constant Register B (TCORB).................................................................... 825
13.3.4 Timer Control Register (TCR).............................................................................. 826
13.3.5 Timer Counter Control Register (TCCR) ............................................................. 827
13.3.6 Timer Control/Status Register (TCSR)................................................................. 829
13.4 Operation ........................................................................................................................... 833
13.4.1 Pulse Output.......................................................................................................... 833
13.4.2 Reset Input ............................................................................................................ 834
13.5 Operation Timing............................................................................................................... 835
13.5.1 TCNT Incrementation Timing .............................................................................. 835
13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs .................. 836
13.5.3 Timing of Timer Output when Compare-Match Occurs....................................... 836
13.5.4 Timing of Compare Match Clear.......................................................................... 837
13.5.5 Timing of TCNT External Reset........................................................................... 837
13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 838
13.6 Operation with Cascaded Connection................................................................................ 839
13.6.1 16-Bit Counter Mode ............................................................................................ 839
13.6.2 Compare Match Count Mode................................................................................ 839
13.7 Interrupt Sources................................................................................................................ 840
13.7.1 Interrupt Sources and DTC Activation ................................................................. 840
13.7.2 A/D Converter Activation..................................................................................... 840
13.8 Usage Notes ....................................................................................................................... 841
13.8.1 Contention between TCNT Write and Clear......................................................... 841
13.8.2 Contention between TCNT Write and Increment ................................................. 842
13.8.3 Contention between TCOR Write and Compare Match ....................................... 843
13.8.4 Contention between Compare Matches A and B .................................................. 844
13.8.5 Switching of Internal Clocks and TCNT Operation ............................................. 844
13.8.6 Mode Setting with Cascaded Connection ............................................................. 846
13.8.7 Module Stop Function Setting .............................................................................. 846