Datasheet

Section 6 Bus Controller (BSC)
Page 178 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Bit Bit Name Initial Value R/W Description
2
1
0
MXC2
MXC1
MXC0
0
0
0
R/W
R/W
R/W
Address Multiplex Select
These bits select the size of the shift toward the
lower half of the row address in row
address/column address multiplexing. In burst
operation on the DRAM/synchronous DRAM
interface, these bits also select the row address
bits to be used for comparison.
When the MXC2 bit is set to 1 while continuous
synchronous DRAM space is set, the address
precharge setting command (Precharge-sel) is
output to the upper column address. For details,
refer to sections 6.7.2 and 6.8.2, Address
Multiplexing.
DRAM interface
000: 8-bit shift
• When 8-bit access space is designated:
Row address bits A23 to A8 used for
comparison
• When 16-bit access space is designated:
Row address bits A23 to A9 used for
comparison
001: 9-bit shift
• When 8-bit access space is designated:
Row address bits A23 to A9 used for
comparison
• When 16-bit access space is designated:
Row address bits A23 to A10 used for
comparison
010: 10-bit shift
• When 8-bit access space is designated:
Row address bits A23 to A10 used for
comparison
• When 16-bit access space is designated:
Row address bits A23 to A11 used for
comparison